technical data 29 counter/divider high-voltage silicon-gate cmos the iw4017b is 5-stage johnson counter having 10 decoded outputs. inputs include a clock, a reset, and a clock inhibit signal. schmitt trigger action in the clock input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. the counter is advanced one count at the positive clock signal transition if the clock inhibit signal is low. counter advancement via the clock line is inhibited when the clock inhibit signal is high. a high reset signal clears the counter to its zero count. use of the johnson counter configuration permits high-speed operation, 2- input decode-gating and spike-free decoded outputs. anti-lock gating is provided, thus assuring proper counting sequence. the decoded outputs are normally low and go high only at their respective decoded time slot. each decoded output remains high for one full clock cycle. a carry-out signal completes one cycle every 10 clock input cycles in the iw4017b. ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package- temperature range; 100 na at 18 v and 25 c ? noise margin (over full package temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply iw4017b ordering information iw4017bn plastic IW4017BDw soic t a = -55 to 125 c for all packages pin assignment logic diagram pin 16 =v cc pin 8 = gnd function table clock clock enable reset output state * l x l no change x h l no change x x h reset counter q0=h, q1-q9=l, c0=h l l advance to next state x l no change x l no change h l advance to next state * carry out=h for q0,q1,q2,q3 or q4=h carry out = l otherwise, x=don?t care
iw4017b 30 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
iw4017b 31 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c25 c 125 c unit v ih minimum high-level input voltage v out =0.5v or v cc - 0.5v v out =1.0v or v cc - 1.0v v out =1.5v or v cc - 1.5v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low -level input voltage v out =0.5v or v cc - 0.5v v out =1.0v or v cc - 1.0v v out =1.5v or v cc - 1.5v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd or v cc 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 a i ol minimum output low (sink) current v in = gnd or v cc u ol =0.4 v u ol =0.5 v u ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minimum output high (source) current v in = gnd or v cc u oh =2.5 v u oh =4.6 v u oh =9.5 v u oh =13.5 v 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 ma
iw4017b 32 ac electrical characteristics (c l =50pf, r l =200k ? , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit f max maximum clock frequency 5.0 10 15 2.5 5 5.5 2.5 5 5.5 1.25 2.5 2.75 mhz t plh , t phl maximum propagation delay, clock to decode output (figure 1) 5.0 10 15 650 270 170 650 270 170 1300 540 340 ns t plh , t phl maximum propagation delay, clock to carry output (figure 1) 5.0 10 15 600 250 160 600 250 160 1200 500 320 ns t tlh , t thl maximum output transition time, carry output or decode output (figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns t plh , t phl maximum propagation delay, reset to carry output or decode output (figure 1) 5.0 10 15 530 230 170 530 230 170 1060 460 340 ns c in maximum input capacitance - 5 pf timing requirements (v cc =5.0v 10%, c l =50pf, input t r =t f =20 ns, r l =200k ? ) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit t w minimum pulse width, clock (figure 1) 5.0 10 15 200 90 60 200 90 60 400 180 120 ns t r, t f maximum input rise and fall times, clock (figure 1) 5.0 10 15 unlimited s t w minimum pulse width, reset (figure 1) 5.0 10 15 260 110 60 260 110 60 520 220 120 ns t rem minimum removal time, reset (figure 1) 5.0 10 15 400 280 150 400 280 150 800 560 300 ns t su minimum setup time, clock inhibit to clock (figure 1) 5.0 10 15 230 100 70 230 100 70 460 200 140 ns
iw4017b 33 figure 1. switching waveforms timing diagram
iw4017b 34 expanded logic diagram
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